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RFD3N08L, RFD3N08LSM
Data Sheet July 1999 File Number
2836.4
3A, 80V, 0.800 Ohm, Logic Level, N-Channel Power MOSFETs
The RFD3N08L and RFD3N08LSM are N-Channel enhancement mode silicon gate power field effect transistors specifically designed for use with logic level (5V) driving sources in applications such as programmable controllers, automotive switching, and solenoid drivers. This performance is accomplished through a special gate oxide design which provides full rated conductance at gate biases in the 3V to 5V range, thereby facilitating true on-off power control directly from logic circuit supply voltages. Formerly developmental type TA09922.
Features
* 3A, 80V * rDS(ON) = 0.800 * Temperature Compensating PSPICE(R) Model * On Resistance vs Gate Drive Voltage Curves * Peak Current vs Pulse Width Curve * UIS Rating Curve * 175oC Operating Temperature * Related Literature - TB334 "Guidelines for Soldering Surface Mount Components to PC Boards"
BRAND
Ordering Information
PART NUMBER RFD3N08L RFD3N08LSM PACKAGE TO-251AA TO-252AA F3N08L F3N08L
Symbol
D
NOTE: When ordering, include the entire part number. Add the suffix 9A to obtain the TO-252AA variant in tape and reel, i.e. RFD3N08LSM9A
G
S
Packaging
JEDEC TO-251AA
SOURCE DRAIN GATE GATE SOURCE
JEDEC TO-252AA
DRAIN (FLANGE)
DRAIN (FLANGE)
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CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures. PSPICE(R) is a registered trademark of MicroSim Corporation. http://www.intersil.com or 407-727-9207 | Copyright (c) Intersil Corporation 1999
RFD3N08L, RFD3N08LSM
Absolute Maximum Ratings
TC = 25oC, Unless Otherwise Specified RFD3N08L, RFD3N08LSM 80 80 10 3 Refer to Peak Current Curve 30 0.2 Refer to UIS Curve -55 to 175 300 260 UNITS V V V A W W/oC
oC oC oC
Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDS Drain to Gate Voltage (RGS = 20K) (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Pulsed Drain Current (Figures 3, 5) (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM Maximum Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .PD Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pulsed Avalanche Energy Rating (Figure 6) (Note 4) . . . . . . . . . . . . . . . . . . . . . . . . .EAS Operating and Storage Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . .TJ, TSTG Maximum Temperature for Soldering Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. TJ = 25oC to 150oC.
Electrical Specifications
PARAMETER
TC = 25oC, Unless Otherwise Specified SYMBOL BVDSS VGS(TH) IDSS TEST CONDITIONS ID = 250A, VGS = 0V (Figure 12) VGS = VDS, ID = 250A (Figure 11) VDS = Rated BVDSS, VGS = 0V VDS = 0.8 x Rated BVDSS, VGS = 0V 125oC MIN 80 1 VGS = 0V to 10V VGS = 0V to 5V VGS = 0V to 1V VDD = 64V, ID = 3A, Ig(REF) = 0.1mA RL = 21.3 (Figures 15, 20, 21) TYP 15 45 22 15 6.8 3.8 0.18 MAX 2.5 25 250 100 0.800 75 45 8.5 4.8 0.24 125 55 15 5.0 100 UNITS V V A A nA ns ns ns ns ns ns nC nC nC pF pF pF
oC/W oC/W
Drain to Source Breakdown Voltage Gate to Threshold Voltage Zero Gate Voltage Drain Current
Gate to Source Leakage Current Drain to Source On Resistance (Note 2) Turn-On Time Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Turn-Off Time Total Gate Charge Gate Charge at 5V Threshold Gate Charge Input Capacitance Output Capacitance Reverse Transfer Characterisics Thermal Resistance, Junction to Case Thermal Resistance, Junction to Ambient
IGSS rDS(ON) t(ON) td(ON) tr td(OFF) tf t(OFF) Qg(TOT) Qg(5) Qg(TH) CISS COSS CRSS RJC RJA
VGS = 10V ID = 3A, VGS = 5V, (Figures 9, 10) VDD = 40V, ID = 3A, RL = 13.3, VGS = 5V, RG = 25, (Figures 13, 15, 18, 19)
VDS = 25V, VGS = 0V, f = 1MHz, (Figure 14)
Source to Drain Diode Ratings and Specifications
PARAMETER Source to Drain Diode Voltage (Note 2) Reverse Recovery Time NOTES: 2. Pulsed: pulse duration = 300s max, duty cycle = 2%. 3. Repetitive rating: pulse width limited by maximum junction temperature. See Transient Thermal Impedance curve (Figure 3). 4. Refer to Intersil Application Notes AN9321 and AN9322. SYMBOL VSD trr ISD = 3A ISD = 3A, dISD/dt = 100A/s TEST CONDITIONS MIN TYP MAX 1.25 85 UNITS V ns
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RFD3N08L, RFD3N08LSM Typical Performance Curves Unless Otherwise Specified
1.2 POWER DISSIPATION MULTIPLIER 1.0 ID, DRAIN CURRENT (A) 125 50 75 100 TC , CASE TEMPERATURE (oC) 0.8 0.6 0.4 0.2 0 0 25 150 175 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 25
50
75 100 125 TC, CASE TEMPERATURE (oC)
150
175
FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE TEMPERATURE
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs TEMPERATURE
1 ZJC, NORMALIZED TRANSIENT THERMAL IMPEDANCE 0.5 0.2 0.1 0.1 0.05 0.02 0.01 SINGLE PULSE 0.01 10-5 t1 t2 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZJC x RJC + TC 10-4 10-3 10-2 10-1 t, RECTANGULAR PULSE DURATION (s) 100 101 PDM
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
20 10 ID, DRAIN CURRENT (A) 100s IDM, PEAK CURRENT CAPABILITY (A)
30
FOR TEMPERATURES ABOVE 25oC DERATE PEAK CURRENT AS FOLLOWS: I = I25 175 - TC 150
10
VGS = 10V
1ms 1 10ms 100ms OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON) 0.1 1 VDSS MAX = 80V TC = 25oC TJ = MAX RATED DC
VGS = 5V TRANSCONDUCTANCE MAY LIMIT CURRENT IN THIS REGION 1 10-5 10-4
TC = 25oC 100 101
10 100 VDS, DRAIN TO SOURCE VOLTAGE (V)
200
10-3 10-2 10-1 t, PULSE WIDTH (s)
FIGURE 4. FORWARD BIAS SAFE OPERATING AREA
FIGURE 5. PEAK CURRENT CAPABILITY
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RFD3N08L, RFD3N08LSM Typical Performance Curves Unless Otherwise Specified (Continued)
20 IAS, AVALANCHE CURRENT (A) 10 If R = 0 tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD) If R 0 tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1] STARTING TJ = 25oC 10 VGS = 10V ID, DRAIN CURRENT (A) 8 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX TC = 25oC
6 VGS = 5V 4 VGS = 4.5V VGS = 4V 2 VGS = 3.5V VGS = 3V
STARTING TJ = 150oC
1 0.001
0.01 0.1 tAV, TIME IN AVALANCHE (ms)
1
0 0 2 4 6 8 VDS, DRAIN TO SOURCE VOLTAGE (V) 10
NOTE: Refer to Intersil Application Notes AN9321 and AN9322. FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING CAPABILITY FIGURE 7. SATURATION CHARACTERISTICS
IDS(ON), DRAIN TO SOURCE CURRENT (A)
10
rDS(ON), ON-STATE RESISTANCE ()
8
PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX VDD = 15V -55oC
2.5 ID = 4A 2 ID = 3A 1.5 ID = 1.5A 1 ID = 0.75A PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX VDD = 15V 2 2.5 3.5 4 4.5 3 VGS, GATE TO SOURCE VOLTAGE (V) 5
6 25oC 4 175oC 2
0.5
0 0 1.5 3 4.5 6 VGS, GATE TO SOURCE VOLTAGE (V) 7.5
0
FIGURE 8. TRANSFER CHARACTERISTICS
FIGURE 9. DRAIN TO SOURCE ON RESISTANCE vs GATE VOLTAGE AND DRAIN CURRENT
3 NORMALIZED ON RESISTANCE 2.5 2 1.5 1 0.5
2 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX VGS = 5V, ID = 3A NORMALIZED GATE THRESHOLD VOLTAGE 1.5 VGS = VDS, ID = 250A
1
0.5
0 -80
-40
0
40
80
120
160
200
0 -80
-40
TJ, JUNCTION TEMPERATURE (oC)
0 40 80 120 160 TJ, JUNCTION TEMPERATURE (oC)
200
FIGURE 10. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE
FIGURE 11. NORMALIZED GATE THRESHOLD VOLTAGE vs JUNCTION TEMPERATURE
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RFD3N08L, RFD3N08LSM Typical Performance Curves Unless Otherwise Specified (Continued)
2.0 ID = 250A NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE 80 1.5 SWITCHING TIME (ns) 100 VDD = 40V, ID = 3A, RL = 13.3 tr
60 tf td(OFF) 20 td(ON)
1.0
40
0.5
0 -80
0 -40 0 40 80 120 160 TJ , JUNCTION TEMPERATURE (oC) 200
0
10
20
30
40
50
RGS, GATE TO SOURCE RESISTANCE ()
FIGURE 12. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE
180 150 C, CAPACITANCE (pF) 120 90 60 CRSS 30 0 CISS
FIGURE 13. SWITCHING TIME vs GATE RESISTANCE
VDS, DRAIN TO SOURCE VOLTAGE (V)
60 RL = 26.67 IG(REF) = 0.1mA VGS = 5V 40 PLATEAU VOLTAGES IN DESCENDING ORDER: VDD = BVDSS VDD = 0.75 BVDSS VDD = 0.50 BVDSS VDD = 0.25BVDSS
3.75
COSS
2.50
20
1.25
0
5 10 15 20 VDS, DRAIN TO SOURCE VOLTAGE (V)
25
0 20
IG(REF) IG(ACT)
t, TIME (s)
80
IG(REF) IG(ACT)
0
NOTE: Refer to Intersil Application Notes AN7254 and AN7260. FIGURE 14. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE FIGURE 15. NORMALIZED SWITCHING WAVEFORMS FOR CONSTANT GATE CURRENT
Test Circuits and Waveforms
VDS BVDSS L VARY tP TO OBTAIN REQUIRED PEAK IAS VGS DUT tP RG IAS VDD tP VDS VDD
+
0V
IAS 0.01
0 tAV
FIGURE 16. UNCLAMPED ENERGY TEST CIRCUIT
FIGURE 17. UNCLAMPED ENERGY WAVEFORMS
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VGS, GATE TO SOURCE VOLTAGE (V)
VGS = 0V, f = 1MHz CISS = CGS + CGD CRSS = CGD COSS CDS + CGD
80
5.00
RFD3N08L, RFD3N08LSM Test Circuits and Waveforms
(Continued)
tON td(ON) tr RL VDS
+
tOFF td(OFF) tf 90%
90%
RG DUT
-
VDD 0
10% 90%
10%
VGS VGS 0 10%
50% PULSE WIDTH
50%
FIGURE 18. SWITCHING TIME TEST CIRCUIT
FIGURE 19. RESISTIVE SWITCHING WAVEFORMS
VDS RL VDD VDS VGS = 10V VGS
+
Qg(TOT)
Qg(5) VDD VGS VGS = 1V 0 Qg(TH) IG(REF) 0 VGS = 5V
DUT Ig(REF)
FIGURE 20. GATE CHARGE TEST CIRCUIT
FIGURE 21. GATE CHARGE WAVEFORMS
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RFD3N08L, RFD3N08LSM PSPICE Electrical Model
SUBCKT RFD3N08L 2 1 3 ;
CA 12 8 4.10e-10 CB 15 14 3.25e-10 CIN 6 8 1.10e-10 DBODY 7 5 DBDMOD DBREAK 5 11 DBREAKMOD DPLCAP 10 5 DPLCAPMOD EBREAK 11 7 17 18 93.57 EDS 14 8 5 8 1 EGS 13 8 6 8 1 ESG 6 10 6 8 1 EVTHRESH 6 21 19 8 1 EZTEMPCO 20 6 18 22 1 IT 8 17 1 LDRAIN 2 5 1e-9 LGATE 1 9 5.8e-9 LSOURCE 3 7 5.8e-9 MOS1 16 6 8 8 MSTRONG M = 0.80 MOS2 16 21 8 8 MWEAK M = 0.20 RBREAK 17 18 RBREAKMOD 1 RDRAIN 50 16 RDRAINMOD 174.2e-3 RGATE 9 20 24.9 RIN 6 8 1e9 RLDRAIN 2 5 10 RLGATE 1 9 58 RLSOURCE 3 7 58 RSCL1 5 51 RSCLMOD 1e-6 RSCL2 5 50 1e3 RSOURCE 8 7 RSOURCEMOD 200.2e-3 RTHRESH 22 8 RTHRESHMOD 1 RZTEMPCO 18 19 RZTEMPCOMOD 1 S1A S1B S2A S2B 6 12 13 8 S1AMOD 13 12 13 8 S1BMOD 6 15 14 13 S2AMOD 13 15 14 13 S2BMOD
rev 5/10/95
LDRAIN DPLCAP 10
RSCL1 +51 5 ESCL 51 50
5 RLDRAIN DBREAK
DRAIN 2
RSCL2
ESG LGATE
6 8 +
RDRAIN
11
EBREAK
GATE 1
EZTEMPCO 20 + 18 22 RGATE RLGATE 9
16 EVTHRESH + 19 8 6 CIN
+ 17 18
DBODY
21 MOS1
MOS2
RIN
LSOURCE 8 RSOURCE 7 3 SOURCE RLSOURCE 18 RZTEMPCO CB + 5 EDS 8 14 IT 19 VBAT + 22 RTHRESH
S1A 12 13 8 S1B CA
14 13
S2A 15 S2B
RBREAK 17
13 + EGS 6 8
VBAT 22 19 DC 1 ESCL 51 50 VALUE = {(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*10),6))} .MODEL DBDMOD D (IS = 9.90e-14 RS = 6.00e-2 TRS1 = 1.42e-3 TRS2 = -3.58e-6 CJO = 1.40e-10 TT = 5.75e-8 M = 0.4) .MODEL DBREAKMOD D (RS = 2.32 TRS1 = 1.03e-3 TRS2 = -6.17e-11) .MODEL DPLCAPMOD D (CJO = 1.13e-10 IS = 1e-30 N = 10 M=0.6) .MODEL MSTRONG NMOS (VTO = 1.773 KP = 1.70 IS = 1e-30 N = 10 TOX = 1L = 1u W = 1u) .MODEL MWEAK NMOS (VTO = 1.496 KP = 2.09 IS = 1e-30 N = 10 TOX = 1L = 1u W = 1u) .MODEL RBREAKMOD RES (TC1 = 8.19e-4 TC2 = 5.9e-7) .MODEL RDRAINMOD RES (TC1 = 1.55e-2 TC2 = 8.58e-5) .MODEL RDSOURCEMOD RES (TC1 = 0 TC2 = 0) .MODEL RSCLMOD RES (TC1 = 0 TC2 = 0) .MODEL RTHRESHMOD RES (TC1 = -5.0e-4 TC2 = -6.0e-6) .MODEL RZTEMPCOMOD RES (TC1 = -1.19e-3 TC2 = 1.12e-6) .MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -5.2 VOFF= -3.2) .MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -3.2 VOFF= -5.2) .MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -0.60 VOFF= 4.4) .MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 4.4 VOFF= -0.60) .ENDS NOTE: 1. For further discussion of the PSPICE model, consult A New PSPICE Sub-circuit for the Power MOSFET Featuring Global Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991.
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RFD3N08L, RFD3N08LSM
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Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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Sales Office Headquarters
NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (407) 724-7000 FAX: (407) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil (Taiwan) Ltd. 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029
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